A wide range of conventional fault models have been used by automated test pattern generation (ATPG) tools to generate test patterns for detecting defects in integrated circuits, such as stuck-at, bridging, inter-cell-opens, and transition faults. While the conventional fault models are efficient in addressing defects between library cell instances, at the ports of library cells, and between the interconnect lines outside of library cells, many intra-cell defects are not detectable by test patterns generated based on the conventional fault models.
Several approaches have been developed to target defects undetectable with the conventional fault models. N-detection based approaches improve the defect coverage by targeting the same fault multiple times under different conditions. However, this typically increases the number of patterns by a factor of N and therefore makes the testing costly. Embedded multi detect based approaches increase the defect coverage by utilizing unused bits in existing test patterns. Unlike the methods based on N-detection, no additional test patterns are needed with the EMD-based approaches. Nevertheless, there exists only a probabilistic relation to actual defects for both techniques. Thus, it is difficult to quantify the additional defect coverage provided by these techniques relative to conventional techniques, and to predict the resulting benefit for future designs. Gate-exhaustive testing approaches are also developed to detect intra-cell defects. Like the N-detection based approaches, however, the gate-exhaustive testing approaches tend to generate a very large number of additional patterns and result in high test costs.
Cell-aware fault models have been developed to directly target intra-cell defects. The methods are discussed in U.S. patent application Ser. No. 12/718,799, entitled “Cell-Aware Fault Model Creation And Pattern Generation,” filed on Mar. 5, 2010, and naming Friedrich Hapke et al. as inventors, which application is incorporated entirely herein by reference (referred to as “U.S. patent application Ser. No. '799” hereinafter). In the methods using cell-aware fault models, intra-cell defects are extracted based on both layout data and transistor-level netlists for a library cells. Analog simulations are applied to determine detection conditions for the defects. The cell-aware based approaches can be applied to various intra-cell defects that can cause stuck-at and time-related faults. For many time-related faults, two-cycle sequential testing is needed. Due to exhaustive simulations in two time frames, however, generation of timing-related cell-aware fault models can lead to long analog fault simulation runtimes.